1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to a method of fabricating an embedded non-volatile memory device.
2. Description of the Prior Art
With increasing integration of electrical circuit elements, the trend of manufacturing semiconductor integrated circuits is to integrate memory array region and high-speed logic circuit elements into a single chip to form an embedded memory. The embedded memory not only significantly reduces the circuit area but also greatly increases the signal processing speed.
SONOS technology has been considered as a replacement for floating gate nonvolatile memory due to the simplicity of the bitcell structure and process, high scalability, low voltage operation, and its immunity to extrinsic charge loss and tail bits. SONOS type flash memory cells are constructed having a charge trapping non-conducting dielectric layer, typically a silicon nitride layer, sandwiched between two silicon dioxide layers (insulating layers). The nonconducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer.
According to the prior art method of fabricating an embedded non-volatile memory, an additional photo mask is necessary to open the memory array region of the embedded memory device merely for channel adjustment of the memory array. This photo mask blocks the peripheral region of the embedded memory device. The channel adjustment of the memory array can be performed by an additional implant stage of lightly doped drain regions or well implant. It is desirable to save manufacture cost of fabricating non-volatile memory devices by simplifying the process steps or reducing the number of photo masks employed in the fabrication of such devices.